Apparatus and method for programming voltage protection in a non-volatile memory system

ABSTRACT

A memory system comprising an array of memory cells, a programming voltage node for receiving a first programming voltage, a memory controller which controls memory programming operations on the array of memory cells, and voltage detection circuitry, operably coupled to the memory controller and the programming voltage node, with the voltage detection circuitry being configured to enable the memory controller to initiate one of the programming operations if the first programming voltage exceeds a first voltage level and to continue the programming operation once the programming operation has been initiated if the first programming voltage drops to a second voltage level and to terminate the programming operation once the programming operation has been initiated if the first programming voltage drops below the second voltage level, with the first voltage level being greater than the second voltage level. And a method of controlling the operation of a memory system which comprises an array of memory cells, the method comprising the steps of providing a first programming voltage, initiating a memory programming operation if the first programming voltage magnitude exceeds a first voltage level, continuing the initiated programming operation if the first programming voltage remains greater in magnitude than a second voltage level, with the first voltage level magnitude being greater in magnitude than the second voltage level, and terminating the initiated programming operation if the first programming voltage magnitude drops below the second voltage level.

TECHNICAL FIELD

[0001] The present invention relates generally to memory systems thatutilize an externally supplied programming voltage.

BACKGROUND OF THE INVENTION

[0002] Integrated circuit memory systems require some form of externallysupplied voltage to carry out various memory operations, includingmemory read, program and erase operations. Typically, voltages ofvarious magnitudes are required to carry out these operations. Memorysystems generally utilize a primary power source having significantcurrent capabilities. The primary power source is typically provided tothe memory by an external source such as a power supply or battery. Theprimary power source, frequently referred to as V_(CC), is connected tothe memory system by way of metal circuit pads formed on the integratedcircuit itself. The primary supply voltage V_(CC) typically has been setto +5 volts, although there has been a trend to reduce the voltage to+3.3 volts and even lower.

[0003] Memory systems also typically utilize voltages other than theprimary supply voltage V_(CC) for carrying out memory operations. By wayof example, memory program operations for flash memory systems typicallyrequire application of a relatively large positive voltage to a selectedone of the word lines of the flash cell array in order to carry out aprogramming operation. Such voltage, typically on the order of +12volts, is sometimes referred to as voltage V_(PP). At the same time, avoltage V_(PPBL) of intermediate value, typically on the order of +7volts, is applied to a selected one of the bit lines of the flash cellarray as part of the programming operation. In most applications, thebit line program voltage is derived from voltage V_(PP) using an on-chipvoltage regulator.

[0004] A typical conventional memory system may have a separate metalcircuit pad for receiving the programming voltage V_(PP) from anexternal source along with the pad for receiving voltage V_(CC). In theevent single power supply operation is desired, a charge pump circuitcan be implemented on the chip so that the externally supplied voltageV_(CC) can be stepped up to voltage V_(PP).

[0005] As an example of a memory system utilizing a programming voltageV_(PP) from an external source, the function of a conventionalnon-volatile flash memory system is shown in the block diagram ofFIG. 1. The core of memory system 1 is an array 12 of memory cells. Theindividual cells in array 12 (not shown) are arranged in rows andcolumns, with there being, in this example, a total of 256K eight bitwords in array 12. Data input and output for the memory system 1 isaccomplished by using an eight bit data bus DQ0-DQ7. The individualmemory cells are accessed by using an eighteen bit address A0-A17, whichis input by means of address pins 13. Nine of the eighteen address bitsare used by X decoder 14 to select a word line associated with the rowof array 12 in which a desired memory cell is located and the remainingnine bits are used by Y decoder 16 to select a bit line associated withthe appropriate column of array 12 in which the desired cell is located.Sense amplifiers 50 are used to read the data contained in a memory cellduring a read operation or during a data verification step in which thestate of a cell is determined after a write or erase operation. Thesense amplifier circuitry and verify circuits compare the state of thecell to a reference state corresponding to a programmed cell or anerased cell, depending upon the operation.

[0006] Writing or erasing of the memory cells in array 12 is carried outby applying the appropriate voltages to the source (source line), drain(bit line), and control gate (word line) of a cell for an appropriatetime period. This causes electrons to tunnel or be injected from achannel region to a floating gate. The amount of charge residing on thefloating gate determines the voltage required on the control gate inorder to cause the device to conduct current between the source anddrain regions. This is termed the threshold voltage of the cell withthere being an erased threshold voltage V_(THE) that is different from aprogrammed threshold voltage V_(THP). Conduction represents an “on” orerased state of the device and corresponds to a logic value of one. An“off” or programmed state is one in which current is not conductedbetween the source and drain regions and corresponds to a logic value ofzero. By setting the threshold voltage of the cell to an appropriatevalue, the cell can be made to either conduct or not conduct current fora given set of applied voltages. Thus, by determining whether a cellconducts current at a given set of applied voltages, the state of thecell (programmed or erased) can be found.

[0007] Memory system 1 contains an internal state machine (ISM) 20 whichcontrols the data processing operations and sub-operations performed onthe memory cells contained in memory array 12. These include the stepsnecessary for carrying out writing, reading and erasing operations onthe memory cells of array 12. In addition, internal state machine 20controls operations such as reading or clearing status register 26,identifying memory system 1 in response to an identification command,and suspending an erase operation. State machine 20 functions to reducethe overhead required of an external processor (not depicted) typicallyused in association with memory system 1.

[0008] To avoid inadvertent programming of the memory device,programming commands (write or erase) consist of two cycles. The firstcycle is a setup command wherein the code corresponding to theprogramming operation is written to the memory chip. To perform thesetup command, the external processor causes the output enable pin{overscore (OE)}to be inactive (high), and the chip enable {overscore(CE)}and write enable {overscore (WE)}pins to be active (low). Theprocessor then places the 8 bit setup command code on data I/O pins 15(DQ0-DQ7) and causes the chip enable {overscore (CE)}and write enable{overscore (WE)}pins to go inactive.

[0009] The command code for the first cycle of a write operation (writesetup) is, for example, either 40 H (1000 0000) or 10 H (0001 0000). Inthe second cycle of a write sequence, after the chip enable {overscore(CE)}and write enable {overscore (WE)}pins are made inactive (high), thedata to be written is placed on the data I/O pins 15 and the address ofthe memory location to be programmed is placed on the address pins 13(A0-A17). The chip enable {overscore (CE)}and write enable {overscore(WE)}are again made active (low) while the programming voltage V_(PP) isapplied to a selected one of the word lines of memory device 1 by way ofthe X decoder 14. In addition, V_(PPBL) is applied to the selected bitlines by Y decoder 16. The rising edge of the chip enable {overscore(CE)}and write enable {overscore (WE)}, whichever is later in time,causes the physical write operation on the memory cell to be initiatedby application of the programming voltages to the cell.

[0010] Similarly, for an erase operation, the first cycle involvessending an erase setup command code such as 20 H (0010 0000) to thememory device 1. The second cycle of an erase, however, involves anerase confirm command code such as D0H (1101 0000) that is written tothe memory device and the rising edge of chip enable {overscore (CE)}andwrite enable {overscore (WE)}initiates the erase cycle which eraseseither the entire memory array 12 or a block of memory locations withinthe array depending upon the functionality designed into the device.

[0011] The commands placed on data I/O pins 15 are transferred to datainput buffer 22 and then to command execution logic unit 24. Commandexecution logic unit 24 receives and interprets the commands used toinstruct state machine 20 to initiate and control the steps required forwriting to array 12 or carrying out another desired operation. When awrite operation is being executed, the data to be programmed into thememory cells is then input using data I/O pins 15, transferred to inputbuffer 22, and then placed in input data latch 30. The input data inlatch 30 is then made available for the cell programming and dataverification operations.

[0012] In the cell programming operation, an internal program pulsecounter (not depicted) is initialized. This counter will keep track ofthe number of programming pulses that have been applied to the cells ofthe word (byte) being programmed. Next, a programming pulse is appliedto the cells of the word located at the address placed on the addresspins 13. The pulse counter is then incremented and a determination ismade as to whether a predetermined maximum number of pulses have beenapplied to the cells. The cells are then checked, during a verify cycle,to determine whether they have, in fact, been programmed. If the cellsare programmed, then the operation has executed successfully. If thecells are not programmed and the maximum number of pulses has not yetbeen reached,-then another programming pulse is applied to the cells.Checking the programming state of the cells is accomplished using thesense amplifiers and associated components 50.

[0013] If the cells are still not programmed when the maximum pulsecount is reached, then a failure has occurred because the maximum numberof programming pulses have been applied to the cells. Depending upon thedesign of the particular memory, the sequence will be terminated or arecord of the failed word will be made and the sequence continued. Thisinformation will then be transferred to the Status Register 26 so thatit can be read by the processor. Once the desired write or eraseoperation sequence is completed, state machine 20 updates 8 bit statusregister 26. The content of the status register 26, in a typical memorydevice, indicates whether a successful write or erase sequence has beencompleted. The contents of status register 26 is transferred to dataoutput buffer 28, which makes the contents available on data I/O pins 15of memory system 1.

[0014] Typically, the programming voltage levels described above arepermitted to vary by 10% from the specified level and the memory devicewill still operate correctly. However, if the voltage level fallsoutside the specified ranges, then the programming function may fail andcorrupt the data stored in the memory cells or a successful programmingoperation would require an unacceptably long period of time. Also, theout-of-specification voltage levels are an indication of failure in thesystem to which the memory device is connected.

[0015] Conventional memory systems are typically only able to detectwhether V_(PP) drops below a preset voltage level such as +10V duringthe programming operation. If V_(PP) drops below the predeterminedlimit, then a voltage sense circuit will sense that an invalid voltagecondition exists. At the beginning of a programming operation, or at anypoint at which the ISM 20 receives an indication that V_(PP) is belowthe predetermined limit, the ISM 20 will abort the operation and set oneor more status bits in the status register 26.

[0016] One common status bit in the status register 26 is a programmingvoltage error flag which indicates whether V_(PP) was outside thespecified limit during the operation. If V_(PP) was outside thespecified range, then the memory device may have aborted the operation,even if V_(PP) dipped out of range only momentarily. If, during theverify cycle after a programming pulse has been applied, the ISM 20detects that the programming voltage was out of the specified range,then it will halt the programming operation and set the programmingvoltage error flag. However, the programming state of the cells willalready have been altered to some degree by the programming pulse.

[0017] Once a programming or erase operation has been completed, a usercan access the status register 26 to determine the status of variousparameters during the operation, including the status of V_(PP). If anerase operation was unsuccessful, the cause of the problem, such as lowvoltage levels, must be eliminated and the procedure repeated. However,if a write operation has been unsuccessful, it is very possible that thedata in the memory system has been corrupted and recovery may not bepossible. In some non-volatile memory systems, an unsuccessful writeattempt may require that at least a portion of the memory array must beerased before another write operation may be performed at the samelocation in the array.

[0018] In addition, V_(PP) voltage levels also typically sag as a resultof the current drawn by the memory system to perform the programmingoperation. As a result, the voltage level of V_(PP) may be above thepredetermined limit prior to the initiation of the programmingoperation, but then drop below the limit as a consequence of theprogramming operation itself.

[0019] A memory system having the capability of monitoring theprogramming voltages and preventing programming operations from beinginitiated that are likely to be unsuccessful or to avoid aborting memoryoperations that have been initiated and will likely completesuccessfully would be very desirable. The present invention providesthis and other capabilities as will become apparent to those skilled inthe art upon a reading of the following Detailed Description of SpecificEmbodiments together with the drawings.

SUMMARY OF THE INVENTION

[0020] The present invention is directed to an apparatus and method fordetecting whether the level of a programming voltage V_(PP) for a memorydevice is within one of several acceptable voltage ranges and preventingthe execution of a programming operation if the programming voltage isnot within an acceptable voltage range.

[0021] In the method of the present invention, when a programmingoperation, such as a write or an erase, is initiated, the programmingvoltage is sampled. If the voltage is found to be outside of apredetermined acceptable voltage range, then the programming operationis blocked from proceeding.

[0022] In the present inventive circuit, when a programming operation isinitiated, an internal control device causes the programming voltageapplied to a connection pad of the memory device to be sampled by avoltage detection circuit. The detection circuit determines whether ornot the sampled voltage is within one of several predetermined rangesthat will guarantee that programming will be successful and generates acorresponding logic signal before the programming voltage is applied tothe memory cells of the memory device. If the voltage level is out ofrange, the internal control device will block the programming operationfrom proceeding in order to prevent the data in the memory from beingcorrupted and will activate an error indication to communicate that theoperation was terminated due to inadequate programming voltage.

[0023] After the programming operation begins, the voltage detectioncircuit applies a different set of acceptable voltage ranges to theprogramming voltage that permits the memory device to continue theprogramming operation even if the programming voltage falls outside ofthe initial range of acceptable voltage levels.

[0024] Further objects and advantages of the present invention willbecome apparent from the following detailed description and accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]FIG. 1 is a functional block diagram of a conventional flashmemory system.

[0026]FIG. 2 is a functional block diagram of a flash memory systemembodying the present invention.

[0027]FIG. 3 is a functional block diagram illustrating an embodiment ofthe program voltage control circuit of the present invention.

[0028]FIG. 4 is a diagram illustrating a voltage detection circuit of anembodiment of the present invention that monitors the programmingvoltage level V_(PP) and produces a signal indicating whether thevoltage is sufficient to program a memory array.

[0029]FIG. 5 is a timing diagram illustrating an example of the signalsinput to and output from the voltage detection circuit of FIG. 4.

[0030]FIG. 6 is a diagram illustrating an embodiment of a noise filter.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0031]FIG. 2 is a block diagram of the components of a flash memorysystem in accordance with the present invention which monitors theprogramming voltage level V_(PP) and produces a signal indicatingwhether the voltage signal is within a range that guarantees thatprogramming will be successful. It is noted that similar referencenumbers in FIGS. 1 and 2 refer to the same signals and components in thetwo figures. Although the invention will be described with reference toa flash memory system, it is important to recognize that the presentinvention can be implemented as part of other types of memory systems.

[0032] As with the memory system of FIG. 1, the core of memory system100 is an array 12 of flash memory cells. The individual memory cells(not shown) are accessed by using an eighteen bit address A0-A17, whichis input by means of address pins 13. Memory system 100 containsinternal state machine (ISM) 120 which controls the data processingoperations and sub-operations performed on memory system 100, such asthe steps necessary for carrying out writing, reading and erasingoperations on the memory cells of array 12. Internal state machine 120is typically implemented in the form of a set of logic gates whoseinputs determine which operations and sub-operations of the memorysystem are carried out and in what order those operations occur.

[0033] Memory system commands are placed on data I/O pins 15, and aretransferred to data input buffer 22 and then to command execution logicunit 24. Command execution logic unit 24 receives and interprets thecommands which are used to instruct state machine 120 to perform thesteps required for writing or erasing array 12 or carrying out anotherdesired operation. Once an operation is completed, state machine 120updates 8 bit status register 26. The contents of status register 26 istransferred to data output buffer 28, which makes the contents availableon data I/O pins 15 of memory system 100.

[0034] As will be explained in greater detail, a program voltage controlcircuit 130 is provided which monitors the magnitude of the programmingvoltage V_(PP) at the initiation of a programming operation. In theevent the voltage is outside of a predetermined acceptable initialvoltage range or set of several acceptable initial voltage ranges, thecircuit functions to interrupt the programming operation before anymemory data can be corrupted.

[0035] During execution of the programming operation, the programvoltage control circuit 130 continues to monitor V_(PP) but applies adifferent predetermined acceptable execution voltage range or set ofseveral acceptable execution voltage ranges such that the ISM 120 willpermit execution to continue so long as V_(PP) is within an acceptableexecution range even though V_(PP) may be outside of any of theacceptable initial voltage ranges.

[0036] In a typical conventional memory system, there is a specifiedminimum set-up time period between the point at which voltage V_(PP)must be within an acceptable initial range and the point at which thememory cells start to become physically programmed while meeting theoperation specifications for the memory system. The programming cycle istypically initiated at the rising edge of the {overscore (WE)}signal. Anexemplary minimum set-up time period is 100 nanoseconds (see the devicespecification for the MT28F002 256K×8 Flash Memory, “Flash Memory DataBook”, Micron Quantum Devices, Inc., 1994). The program voltage controlcircuit 130 of the present invention must sense the programming voltageV_(PP) within the set-up time and abort the programming sequence if theV_(PP) is not within a predetermined voltage range, as will beexplained.

[0037] The program voltage control circuit 130 is connected to theprogramming power supply pad and receives timing signals 110 from statemachine 120 and returns a voltage level signal 115 to state machine 120.In the course of the set-up and execution of a programming operation,the ISM 120 will generate timing signals 110 that will cause the programvoltage control circuit 130 to sample the programming voltage levelV_(PP) present at the programming power supply pad. Voltage reference170 provides a reference voltage level 172 that program voltage controlcircuit 130 uses for comparison purposes.

[0038] The program voltage control circuit 130 will subsequentlygenerate a voltage level OK (LevelOK) signal 115 that the ISM 120 willcheck before proceeding to execute the programming operation. If thevoltage level signal 115 indicates that the programming voltage is notwithin an acceptable initial voltage range, then the ISM 120 will blockthe write operation and an error indication will be set in the 8 bitstatus register 26. If the voltage level signal 115 indicates that theprogramming voltage is within an acceptable initial voltage range, thenISM 120 proceeds to perform the programming operation.

[0039] The program voltage control circuit also supplies the word lineprogramming voltage V_(PPWL) and bit line programming voltage V_(PPBL)to the V_(PP) switch 18 which further relays these voltages to the Xdecoder 14 and Y decoder 16, respectively, for application to the cellsof memory array 12.

[0040]FIG. 3 is a block diagram of the program voltage control circuit130. The program voltage control circuit 130 is connected to theexternally supplied programming voltage V_(PP) which is received byvoltage detection circuit 300. The voltage detection circuit 300 alsoreceives control signal 110 from state machine 120 which cause it tosample the voltage level of V_(PP) in preparation for a write operation.The voltage detection circuit 300 generates and provides LevelOK signal115 to state machine 120 which indicates whether V_(PP) is within anacceptable voltage range. Voltage detection circuit 300 furthergenerates a SELECT CHARGE PUMP signal which, when the voltage level ofV_(PP) is insufficient to directly program memory cells, but is within avoltage range sufficient to permit charge pump circuit 310 to produce anappropriate programming voltage level. As will be explained, SelectCharge Pump signal is active only when voltage V_(PP) has a magnitude ofless than +6 volts and more than +3 volts. When active, the SelectCharge Pump signal will cause switch 330 to connect the input of chargepump circuit 310 to V_(PP) while simultaneously causing switch 340 toconnect the V_(PPWL) input of voltage regulator 320 to the output ofcharge pump circuit 310. The output of voltage regulator 320 then usesthe voltage level output from charge pump circuit 310 (+12 volts, forexample) to generate the appropriate voltage level for V_(PPBL) (+7voltage, for example).

[0041] Conversely, when the voltage level of V_(PP) is high enough todirectly supply the programming voltage levels (over +10volts, forexample), then voltage detection circuit 300 causes switch 330 todisconnect charge pump circuit 310 from V_(PP) and directly couplesV_(PP) to V_(PPBL) through switches 330 and 340 to the input of voltageregulator 320. V_(PP) is then used to directly provide V_(PPWL) anddrive voltage regulator 320 to produce V_(PPBL). In some applications,it may be desirable to provide a further voltage regulator (notdepicted) for generating voltage V_(PPWL). In that event the regulatorwould have an input connected to the output of switch 340 as isregulator 320 so that voltage V_(PPWL) is regulated in the same manneras is voltage V_(PPBL). This will ensure that V_(PPWL) does not exceed amaximum specification value in the event input V_(PP) becomes too large.Note that any such regulator used to produce V_(PWL) will cause a dropin voltage so that it may be necessary provide another charge pumpcircuit between the regualtor and switch 340. Since voltage V_(PPWL) isconnected to the word lines which draw little current, the currentrequirements of such an additional charge pump circuit will be small.

[0042] In the event voltage V_(PP) is less than +10 volts, the voltagecannot be used to directly program the memory, so that a charge pumpcircuit, such as circuit 310 must be used. However, if the voltage isgreater than +6 volts, the voltage still cannot be used since a voltageof this magnitude is likely to damage the CMOS circuitry typically usedto implement charge pump circuit ₃₁₀. The damage typically is causedwhen the CMOS inverters of the pump 310 enter a snap back mode ofoperation when switching from one state to another. Thus, it isnecessary to ensure that no voltage greater than +6 volts is applied tocharge pump circuit ₃₁₀ by making the Select Charge Pump signal inactivewhen V_(PP) is greater than +6 volts.

[0043] An embodiment of voltage detection circuit 300 of the presentinvention is shown in FIG. 4. The components of timing signals 110supplied by ISM 120 are shown as Enable1 110 a, Enable2 110 b andConnect 110 c.

[0044] The voltage detection circuit 300 utilizes a dual resistanceladder to sample the programming voltage. The low resistance legincludes resistors RA, RB, RC and RD which have low resistance values inseries with transistor 132 that permits current to flow from programmingvoltage V_(PP) pad to ground when the Enable1 signal 110 a is active.The low resistance values permit rapid initialization of a series ofvoltage sampling nodes N1, N2, and N3 which are each connected throughtransistors 142, 144 and 146 respectively to the inputs of voltagecomparators 148, 150 and 152 respectively.

[0045] Transistors 134, 136 and 138 connect the low resistance leg tosampling nodes N1, N2 and N3 respectively and are controlled by Connectsignal 110 c which, when inactive, isolates the low resistance leg fromthe nodes. The higher current of the low resistance leg rapidly chargesthe sample nodes N1-3 to permit the programming voltage to be quicklysampled. By inactivating Connect signal 110 c and enable signal 110 a,the relatively high current in the low resistance leg can be shut-offonce voltage sampling nodes N1-3 are charged.

[0046] The resistors RA, RB, RC and RD may also be selected to haverelative ratios that result in a set of acceptable initial voltageranges that produce an active LevelOK signal 115 while Enable1 110 a andConnect 110 c are active that are different from a set of acceptableexecution voltages that apply when only Enable2 110 b is active.

[0047] The high resistance leg of the resistance ladder consists of highmagnitude resistors R1, R2, R3 and R4 connected in series withtransistor 140 controlled by the Enable2 signal 110 b. The points atwhich the resistors of the high resistance leg meet are the voltagesampling nodes N1-3. The greater resistance of the high resistance legresults in a relatively low current draw. Consequently, the voltage atthe sample nodes N1-3 can be maintained at a lower current level byleaving Enable2 110 b active after Enable1 110 a and Connect 110 c havebeen deactivated.

[0048] Some sample resistance values for resistors RA, RB, RC and RD inan embodiment of the present invention are 6 k Ω, 4 k Ω, 10 k Ω and 10 kΩ respectively. The corresponding values for resistors R1, R2, R3 and R4are 60 k Ω, 40 k Ω, 100 k Ω and 100 k Ω, respectively. These values areapproximations based upon n-well resistors and will vary depending uponthe semiconductor technology used and the details of the design of thespecific memory system. What is notable here is that the resistancevalues of R1, R2, R3 and R4 are an order of magnitude greater than theresistance values of RA, RB, RC and RD in order to obtain a lowercurrent draw through the high resistance leg.

[0049] The ratios of the given resistor values may also be adjustedbetween the two legs in order to obtain an active LevelOK signal 115 fordifferent voltage ranges of V_(PP) when both Enable1 110 a and Enable2110 b are active and when only Enable2 110 b is active. When onlyEnable2 110 b is active, then the voltage ranges that produce an activeLevelOK signal 115 are determined by the relative ratios of R1, R2, R3and R4 because the low voltage leg resistors RA, RB, RC and RD areisolated from the sample nodes N1, N2 and N3. Therefore, a different setof acceptable execution voltage ranges can be defined with theappropriate selection of resistance values for R1, R2, R3 and R4.

[0050] Transistors 142, 144 and 146 protect the comparators 148, 150 and152 from overvoltage conditions that may occur at nodes N1, N2 and N3.The gates of the transistors are connected to the operational supplyvoltage V_(CC). The reference voltage 172 is typically around 2 Volts.As long as the voltage V_(CC) at the gates of transistors 142, 144 and146 is high enough to transfer 2 Volts from the drain to the source ofeach transistor, the logic of the comparators 148, 150 and 152 willfunction properly. However, if any of the voltages at nodes N1, N2 andN3 rises above the supply voltage level, then the voltage at the inputto the comparators will be limited to the supply voltage level less thethreshold voltage of the transistor. Since Enable1 110 a and Enable2 110b are inactive during non-programming operations, nodes N1-3 will bepulled up toward the voltage at V_(PP). V_(PP) could be at 12V or higherduring non-programming modes, as well as during programming operations.This means that nodes N1-3 could be at high voltage levels for extendedperiods of time. Transistors 142, 144 and 146 thus act as voltagelimiters that protect comparators 148, 150 and 152 from long-term highgate or oxide voltage exposure damage.

[0051] The Select Charge Pump signal is generated by combining thesignal Gt3vLev with the inverse of signal Gt6Lev using inverter ₁₅₇together with AND gate ₁₅₉. Thus, as previously noted, the Select ChargePump signal is active only when voltage V_(PP) is less than +6 volts andmore than +3 volts.

[0052] The timing diagram in FIG. 5 illustrates an example of a timingscheme for the present invention and will be used to further describethe function of the circuit in FIG. 4.

[0053] First, a write or erase setup command is written to the memorydevice 100 during a write pulse occurring on {overscore (WE)}betweentime t0 and time t1 in FIG. 5. In response to the rising edge of thewrite enable {overscore (WE)}signal at time t1, ISM 120 will activateEnable1 110 a, Enable2 110 b and Connect 110 c. This permits current toflow from the V_(PP) pad through both legs of the resistance ladder andrapidly charge the capacitances of sampling nodes N1, N2 and N3 duringthe period from t1 to t2. The voltages present at the nodes N1-3 mayresult in logic level changes in the LevelOK output 115 of the voltagedetection circuit 300. However, LevelOK 115 will not be sampled by ISM120 until later in the write/erase sequence.

[0054] As discussed above, there is a set-up time during which V_(PP)must be within a predetermined voltage range specified for the memorydevice 100, such as between +3 and +6V or over +10V. A common devicespecification for the set-up time is 100 nanoseconds. This correspondsto 100 nanoseconds before t3. At t3, the Enable1 110 a and Connect 110 csignals go inactive thereby isolating the low resistance leg (RA, RB, RCand RD) from the high resistance leg (RI, R2, R3 and R4). However,Enable2 110 b remains active and current from the V_(PP) pad continuesto flow in the high resistance leg to maintain the voltage samples atnodes N1-3.

[0055] Enable1 110 a and Connect 110 c will remain active until t3.Since R1-R4 have much higher impedances than RA-RD, the ratio of theresistors of RA-RD primarily determines the logic value of the LevelOK115 signal upon initiation of programming at t3. By t3, the LevelOK 115signal must be at a valid logic value reflecting the conditions at theV_(PP) pad and the ISM 120 will either proceed with the programmingoperation or block programming and issue an error indication based onthe value of LevelOK 115. Table 1 shows an example of the relationshipbetween V_(PP) and the logical value of LevelOK 115. (The entries inTable 1 with “---” in the LevelOK column indicate voltage conditionswhich are not possible e.g. the entry in the second row where V_(PP) isgreater than +10V and thus cannot also be less than +3V and +6V.) TABLE1 LEVEL > + 3 VOLTS > + 6 VOLTS > + 10 VOLTS OK 0 0 0 N 0 0 1 — 0 1 0 —0 1 1 — 1 0 0 Y 1 0 1 — 1 1 0 N 1 1 1 Y

[0056] Beginning at t1, the voltage at node N1 is connected throughtransistor 144 to the positive input of comparator 148. The voltage atN1 is compared to the reference voltage 172 supplied to the negativeterminal of comparator 148 from voltage reference 170. The referencevoltage 172 and the resistance values for RA-D and R1-4 are selectedsuch that, when V_(PP) is above a predetermined voltage level (+10V inthis example), then the output of comparator 148 goes high and the logicsignal Gt10vLev will propagate through inverter 156 and NAND gate 160 tothe input of NAND gate 154. If V_(PP) is above +10V then the output ofcomparator 152 will also be high thus forcing the output of NAND gate154 low. Transient signal changes appearing at the outputs ofcomparators 148, 150 and 152 that are caused by voltage spikes in V_(PP)are prevented from being propagated through inverter 162 and into theLevelOK signal 115 by the noise filter 158. In addition, resistors R1-4can be fabricated to have capacitance, such as when the resistors arefabricated as n-well semiconductor devices. The large area required toachieve high resistance results in high capacitance. Because of thelarge resistance and capacitance of the devices, a filter with a largeRC constant is created which also tends to filter out transient noise inthe voltage at V_(PP).

[0057] In a manner similar to the events at N1, the voltage at N2 passesthrough transistor 144 to the input of comparator 150 to produceGt6vLev. For this example, the reference voltage 172 and the resistancevalues for RA-D and R1-4 are selected such that when V_(PP) is above+6V, then Gt6vLev will be high. If the voltage is less than +10V, thenGt10vLev will be low resulting in the output of NAND gate 160 beingforced low. This low value will propagate to the LevelOK 115 outputwhich will be forced low. The low logic level on LevelOK indicates thatthe voltage at V_(PP) is too low to be used directly to program thecells in memory array 12 and too high to use a charge-pump to generatethe programming voltage for the cells. The ISM 120, when it observes thelow logic output from LevelOK 115, will prohibit the programmingoperation from proceeding and a V_(PP) failure bit will be set in thestatus register.

[0058] Likewise, the voltage at N3 passes through transistor 146 to thepositive input of comparator 152 for sampling. As with nodes N1 and N2above, the reference voltage 172 and resistance values RA-D and R1-4 areselected such that Gt3vLev will be high when V_(PP) is above +3V. WhenGt3vLev is low, the voltage at V_(PP) is too low to either provide aprogramming voltage level or supply sufficient voltage to permit acharge pump to generate a programming voltage level and LevelOK 115 willbe forced low to signal the ISM 120 to block further execution of theprogramming operation. If Gt3vLev is high, but Gt6vLev is low,indicating that the voltage is greater than +3V but less than +6V sothat a charge pump can operate, then both inputs to NAND gate 154 willbe high which will result in LevelOK 115 being high thus signalling theISM 120 that V_(PP) is at least sufficient to operate the charge pumpand the ISM 120 will proceed with the programming operation.

[0059] An example of an embodiment of the noise filter 158 is shown inFIG. 6. The output of NAND gate 154 is split into two signals, one whichfeeds directly into an input of AND gate 504 and the other which isinput to delay circuit 502. When a valid voltage condition exists, theoutput of NAND gate 154 will be low causing the output of AND gate 504to also be low. If a transient condition in V_(PP) causes the output ofNAND gate 154 to become high, then the output of delay 502 will remainlow for a predetermined delay time and thus force the output of AND 504to also be low. If the output of NAND gate 502 returns to a low valuebefore the high signal is propagated to the output of delay 502, thenthe output of AND 504 will not reflect the change in signal from NANDgate 154.

[0060] In addition, as discussed above, because the low resistance legis isolated from the high resistance leg by transistors 134, 136, and138 controlled by the Connect signal 110 c, the values of RA, RB, RC andRD can be selected to be proportionately different from one another thanR1, R2, R3 and R4. By selecting different relative proportions for thetwo legs, the acceptable initial voltage ranges can be made differentfrom the acceptable execution voltage ranges. In other words, theresistors can be chosen such that different voltage ranges result inLevelOK 115 going active for an initial sampling through the lowresistance leg than for the high resistance leg. In this manner, theprogramming voltage can be subject to higher requirements at thebeginning of the programming operation in order to prevent a programmingoperation from being initiated which will fail but also compensate forthe voltage sags that will occur in V_(PP) due to the current drawn whenthe programming pulses are applied. After execution has commenced, thememory cells have already been altered and it is desirable to attempt tocontinue the operation in case it is able to complete successfully.

[0061] Once the programming operation has commenced at t3, it may beundesirable to abort the operation and produce an error indication inresponse to a momentary sag in V_(PP) if the fluctuation is minor andtherefore unlikely to result in failure of the write or erase operationon the memory array 12. Also, the programming operation may be able tocomplete successfully by simply applying a larger number of programmingpulses to the cells. Because only Enable2 11 b is active after t3, theratio of resistors R1-R4 determines the range of voltages that producean active LevelOK 115 signal. R1-R4 may therefore be selected to obtaina different range of acceptable voltages during the time period after t3in which execution of the programming operation takes place. By placingmore stringent restrictions on the range of acceptable voltages at theinitiation of a programming operation, t3 in the present example, thanduring execution of the operation, programming operations can be carriedout despite the presence of transitory fluctuations in the programmingvoltage.

[0062] The terms and expressions which have been employed herein areused as terms of description and not of limitation, and there is nointention in the use of such terms and expressions of excludingequivalents of the features shown and described, or portions thereof, itbeing recognized that various modifications are possible within thescope of the invention claimed.

What is claimed is:
 1. A memory system comprising: an array of memory cells; a programming voltage node for receiving a first programming voltage; a memory controller which controls memory programming operations on the array of memory cells; and voltage detection circuitry, operably coupled to the memory controller and the programming voltage node, with the voltage detection circuitry being configured to enable the memory controller to initiate one of the programming operations if the first programming voltage magnitude exceeds a first voltage level and to continue the programming operation once the programming operation has been initiated if the first programming voltage magnitude drops to a second voltage level and to terminate the programming operation once the programming operation has been initiated if the first programming voltage magnitude drops below the second voltage level, with the first voltage level being greater than the second voltage level.
 2. The memory system of claim 1 wherein the voltage detection circuitry is further configured to enable the memory controller to initiate one of the programming operations if the first programming voltage magnitude exceeds a third voltage level and to continue a programming operation once the programming operation has been initiated if the first programming voltage magnitude drops to a fourth voltage level, and to terminate the programming operation once the programming operation has been initiated if the first programming voltage magnitude drops below the fourth voltage, with the third voltage level being greater than the fourth voltage level and less than the first and second voltage levels.
 3. The memory system of claim 2 wherein the voltage detection circuitry is further configured to prevent the memory controller from initiating memory operations when the first programming voltage magnitude exceeds a fifth voltage level and is less than the first voltage level, with the first voltage level being greater than the fifth voltage level and the fifth voltage level being greater than the third voltage level.
 4. The memory system of claim 3 wherein the memory system is implemented in integrated circuit form and the programming voltage node comprises a metal pad of the integrated circuit which receives the first programming voltage from a source external to the integrated circuit.
 5. The memory system of claim 4 wherein the memory cells are non-volatile memory cells.
 6. A method of controlling the operation of a memory system which comprises an array of memory cells, said method comprising the following steps: providing a first programming voltage; initiating a memory programming operation if the first programming voltage magnitude exceeds a first voltage level; continuing the initiated programming operation if the first programming voltage remains greater than a second voltage level, with the first voltage level being greater in than the second voltage level; and terminating the initiated programming operation if the first programming voltage magnitude drops below the second voltage level.
 7. The method of claim 6 comprising the further steps of: initiating a memory programming operation if the first programming voltage magnitude exceeds a third voltage level; continuing the initiated programming operation if the first programming voltage magnitude remains above a fourth voltage level; and terminating the initiated programming operation if the first programming voltage magnitude drops below the fourth voltage level, with the third voltage level being greater in magnitude than the fourth voltage level and smaller in magnitude than the first and second voltage levels.
 8. The method of claim 7 wherein the step of initiating a memory programming operation if the first programming voltage magnitude exceeds a first voltage level comprises the step of applying the first programming voltage to the memory cells to be programmed.
 9. The method of claim 8 wherein the step of initiating a memory programming operation if the first programming voltage magnitude exceeds a third voltage level includes the steps of generating a second programming voltage having a magnitude greater than the second voltage level and applying the second programming voltage to the memory cells to be programmed.
 10. The method of claim 9 comprising the further step of preventing initiation of the programming operations in the event the first programming voltage has a magnitude which is less than the first voltage level and greater than a fifth voltage level, with the fifth voltage level being greater than the third voltage level and less than the first voltage level.
 11. The method of claim 10 comprising the further steps of generating a reference voltage, generating, prior to the step of initiating the programming operation, a first intermediate voltage having a magnitude equal to the reference voltage when the first programming voltage magnitude is at the first voltage level and generating, subsequent to the step of initiating the programming operation, a second intermediate voltage having a magnitude equal to the reference voltage when the first programming voltage magnitude is at the second voltage level.
 12. The method of claim 11 comprising the further steps of generating, prior to the step of initiating the programming operation, a third intermediate voltage having a magnitude equal to the reference voltage when the first programming voltage magnitude is at the third voltage level and generating, subsequent to the step of initiating the programming operation, a fourth intermediate voltage having a magnitude equal to the reference voltage when the first programming voltage magnitude is at the fourth voltage level.
 13. A memory system comprising: an array of memory cells; a memory controller which controls memory programming operations of the memory system; a programming voltage node configured to receive a first programming voltage; a voltage detection circuit, operably coupled to the programming voltage node and the memory controller, said voltage detection circuit configured to detect when the first programming voltage is within a first voltage range having a lower limit and within a second voltage range having an upper limit, with the magnitude of the lower limit of the first voltage range being greater than the magnitude of the upper limit of the second voltage range, with the voltage detection circuit being further configured to inhibit the memory controller from initiating memory programming operations when the first programming voltage is outside the first and second voltage ranges and to enable the memory controller to perform memory programming operations when the first programming voltage is within one of the first and second voltage ranges.
 14. The memory system of claim 13 wherein the voltage detection circuit comprises: a voltage divider circuit operably coupled to the programming voltage node and configured to produce a first intermediate voltage at a first node when the first programming voltage is at the lower limit of the first voltage range and configured to produce a second intermediate voltage at a second node when the first programming voltage is at the upper limit of the second voltage range; a first comparator having a first input coupled to the first node; and a second comparator having a first input coupled to the second node.
 15. The memory system of claim 14 wherein the second voltage range has a lower limit that is less than the magnitude of the second voltage range upper limit and wherein the voltage divider is further configured to produce a third voltage at a third node and wherein the voltage detection circuit further comprises a third comparator circuit having a first input coupled to the third node.
 16. The memory system of claim 15 wherein the voltage detection circuit further includes combinational logic circuitry operably coupled to outputs of the first, second and third comparators and the memory controller so that the memory controller is inhibited from initiating programming operations if the first programming voltage at the programming voltage node falls outside the first and second voltage ranges.
 17. The memory system of claim 16 wherein the first, second and third voltages are of a same magnitude.
 18. The memory system of claim 17 wherein the voltage detection circuit further comprises a voltage reference circuit which is configured to generate a reference voltage and wherein the first, second and third comparator circuits each have a second input configured to receive the reference voltage.
 19. The memory system of claim 18 wherein the first, second, third and reference voltages are of the same magnitude.
 20. A memory system comprising: an array of memory cells; a memory controller which controls memory programming operations of the memory system; a programming voltage node configured to receive a first programming voltage; a voltage detection circuit, operably coupled to the programming voltage node and the memory controller, said voltage detection circuit comprising a voltage divider circuit switchable between a first state and a second state, with the voltage divider circuit being configured to produce, when in the first state, a first intermediate voltage at a first node when the first programming voltage is at a first level, a second intermediate voltage at a second node when the first programming voltage is at a second level and a third intermediate voltage at a third node when the first programming voltage is at a third level and with the voltage divider circuit being configured to produce, when in the second state, the first intermediate voltage at the first node when the first programming voltage is at a fourth level, the second intermediate voltage at the second node when the first programming voltage is at a fifth level, and the third intermediate voltage at the third node when the first programming voltage is at a sixth level, with the first voltage level being greater than the fourth voltage level; and said voltage detection circuit further comprising control circuitry, operably coupled to the first node of the voltage divider circuit, said control circuitry being configured to enable the memory controller to initiate a memory program operation when the first programming voltage exceeds the first level and to cause the memory controller to terminate an initiated program operation when the first programming voltage drops below the fourth level.
 21. The memory system of claim 20 wherein the voltage divider circuit is further configured to produce, when in the second state, the second intermediate voltage at the second node when the first programming voltage is at a fifth level and the third intermediate voltage at the third node when the first programming voltage is at a sixth level, with the sixth voltage level being greater than the third voltage level, with said the control circuitry being operably coupled to the third node and configured to enable the memory controller to initiate a memory program operation when the first programming voltage exceeds the third voltage level and to cause the memory controller to terminate an initiated memory programming operation when the first programming voltage drops below the sixth voltage level.
 22. The memory system of claim 27 wherein the control circuit comprises a first comparator circuit having a first input coupled to the first node, a second comparator circuit having a first input coupled to the second node and a third comparator circuit having a first input coupled to the third node.
 23. The memory system of claim 22 wherein control circuit further comprises combinational logic circuitry operably coupled to outputs of the first, second and third comparator circuits, with said combinational logic circuitry configured to enable the memory controller to initiate and terminate the memory programming operations.
 24. The memory structure of claim 23 wherein the voltage divider circuit consumes more electrical power in the first state than in the second state.
 25. The memory structure of claim 24 wherein the voltage divider circuit consumes an order of magnitude more electrical power in the first state than in the second state.
 26. The memory system of claim 25 wherein the control circuit further comprises a voltage reference circuit configured to produce a reference voltage, with the first, second and third comparator circuits each having a second input coupled to receive the reference voltage.
 27. The memory system of claim 26 wherein the first, second and third intermediate voltages have a magnitude equal to a magnitude of the reference voltage.
 28. The memory system of claim 20 wherein the voltage divider circuit comprises a first voltage divider circuit which comprises a first impedance coupled intermediate the programming voltage node and the third node, a second impedance coupled intermediate the third and second nodes and a third impedance coupled to the first node and a second voltage divider circuit which comprises a fourth impedance coupled intermediate the programming voltage node and the third node and a second voltage divider circuit which comprises a fifth, sixth seventh and eighth impedances coupled in series and wherein the voltage divider circuit further comprises switching circuitry configured to selectively couple a junction formed by the fifth and sixth impedances to the third node, a junction formed by the sixth and seventh impedances to the second and a junction formed by the seventh and eighth impedances to the first node when the voltage divider circuit is in first state and to decouple the junctions from the first, second and third nodes when the voltage divider circuit is in the second state.
 29. A memory system comprising: an array of memory cells; a memory controller which controls memory operations of the memory system; a programming voltage node for receiving a programming voltage; a voltage detection circuit comprising first and second voltage divider circuit, with the first voltage divider circuit comprising first and second impedances coupled in series so as to form a common first node and with the second voltage divider circuit comprising third and fourth impedances coupled in series, with the voltage detection circuit further comprising a first comparator circuit having an input coupled to the first node and switching circuitry configured to selectively couple and decouple a junction formed by the third and fourth impedances to the first node and control circuitry operably coupled to an output of the first comparator circuit, with the control circuit being configured to enable the memory controller to initiate a programming operation when the programming voltage exceeds a first voltage level and the switching circuitry couples the junction of the third and fourth impedances to the first node and configured to cause an initiated programming operation to terminate when the programming voltage drops below a second level and the switching circuitry decouples the junction of the third and fourth impedances from the first node.
 30. The memory system of claim 29 wherein the first and second voltage dividers are coupled to the programming voltage node and wherein the voltage detection circuit further comprises a reference voltage circuit configured to generate a reference voltage, with the first comparator circuit having a second input coupled to the reference voltage circuit.
 31. The memory circuit of claim 30 wherein the first voltage level is greater in magnitude than the second voltage level.
 32. The memory circuit of claim 31 wherein the first voltage divider circuit has a series impedance which is at least one-half a series impedance of the second voltage divider circuit.
 33. The memory circuit of claim 32 wherein the first voltage divider circuit further comprises a fifth impedance coupled to the second impedance to form a second node and the second voltage divider circuit further comprises a sixth impedance coupled to the fourth impedance and wherein the switching circuitry is further configured to selectively couple and decouple a junction formed by the sixth and fourth impedances to the second node and wherein the voltage detection circuit further comprises a second comparator circuit having a first input coupled to the second node and a second input coupled to the reference voltage circuit and wherein the control circuitry is operably coupled to an output of the second comparator circuit, with the control circuitry being configured to enable the memory controller to initiate a programming operation when the programming voltage exceeds a third voltage level and to cause the memory controller to terminate an initiated programming operation when the programming voltage drops below a fourth voltage level, with the third voltage level being greater in magnitude than the fourth voltage level.
 34. A method of controlling operation of a memory system comprising the following steps: monitoring the magnitude of a first programming voltage; initiating a memory programming operation only in the event both a memory program command is detected and the first programming voltage falls within a first or a second voltage range, with the first voltage range having a lower limit and the second voltage range having an upper limit, with the lower limit being of greater magnitude than the upper limit.
 35. The method of claim 34 wherein the memory operation is initiated by application of the first programming voltage to a memory cell array of the memory system if the first programming voltage is in the first voltage range and is initiated by application of a second programming voltage different from the first programming voltage if the first programming voltage is in the second voltage range.
 36. A method of controlling operation of a memory system comprising the following steps: providing first and second voltage divider circuits; applying a first programming voltage to a first programming voltage node; coupling the first and second voltage dividers circuits in parallel between the first programming voltage node and a circuit common so as to generate first and second intermediate voltages at respective first and second divider nodes when the applied first programming voltage is at respective first and second voltage levels; comparing the first and second intermediate voltages to a reference voltage; initiating a programming operation when the applied first programming voltage falls within a first voltage range having a lower limit defined by the first voltage level or a second voltage range having an upper limit defined by the second voltage level; and terminating the initiated programming operation in the event the first programming voltage falls outside a third or fourth voltage range, with the third voltage range having a lower limit defined by a third voltage level and with the fourth voltage range having a lower limit defined by a fourth voltage level, with the first voltage level being greater than the third voltage level, the third voltage level being greater than the second voltage level and the second voltage level being greater than the fourth voltage level.
 37. The method of claim 36 comprising the step, subsequent to the step of initiating the programming operation, of decoupling the second voltage divider from the divider nodes so as to cause a third intermediate voltage to be generated at the first divider node and a fourth intermediate voltage to be generated at a third divider node when the first programming voltage is at the third and fourth voltage levels, respectively.
 38. The method of claim 37 further including the step of comparing the third and fourth intermediate voltages to a reference voltage.
 39. The method of claim 38 wherein the first voltage divider circuit has a series impedance at least twice as great as a series impedance of the second voltage divider.
 40. A memory system comprising: an array of memory cells; a memory controller which controls memory operations on the array of memory cells, including memory program operations; a programming voltage node configured to receive a programming voltage; voltage sense circuitry, operably coupled to the programming voltage node and configured to sense a magnitude of the programming voltage; program interrupt circuitry which causes the memory controller to terminate one of the memory programming operations should the programming voltage magnitude fall outside a first or a second separate programming voltage ranges; wherein the voltage sense circuitry comprises a first resistor network, with the first resistor network comprising a plurality of resistors connected to form a voltage divider, with the first resistor network having a first node for coupling to the programming voltage node and a second node for coupling to a circuit common, and a third node where a first divided voltage is produced when the programming voltage is at a lower limit of the first programming voltage range, a fourth node where a second divided voltage is produced when the programming voltage is at a lower limit of the second programming voltage range.
 41. The memory system of claim 40 wherein the voltage sense circuitry comprises a first comparator circuit having a first input coupled to the third node of the first resistor network and a second input coupled to a reference voltage.
 42. The memory system of claim 41 wherein the voltage sense circuitry comprises a second comparator circuit having a first input coupled to the fourth node of the first resistor network and a second input coupled to the reference voltage.
 43. The memory system of claim 42 wherein the voltage sense circuitry includes a third comparator circuit having a first input coupled to the fifth node of the first resistor network and a second input coupled to the reference voltage.
 44. The memory system of claim 43 wherein the program interrupt circuitry comprises logic circuitry which logically combines outputs of the first, second and third comparator circuits.
 45. The memory system of claim 40 wherein the voltage sense circuitry further comprises a second resistor network comprising a plurality of resistors connected to form a voltage divider and switching circuitry for connecting the second resistor network in parallel with the first resistor network and disconnecting the second resistor network from the first resistor network, with the first resistor network having a series resistance that is at least twice as great as a series resistance of the second resistor network. 